1. Field of the Invention
This invention generally relates to power amplifiers, and more specifically, to a cascode-cascade power amplifier assembly.
2. Description of Related Art
Orthogonal frequency division multiplexing (OFDM) is commonly adopted by modern high-speed wireless communication systems in order to achieve the objective of high transmission data rate. However, the major drawbacks of the OFDM systems are the high peak-to-average power ratio (PAPR) and large dynamic range of the transmit signal due to the utilization of a multi-carrier modulation method. The power amplifier is found to achieve the maximum power efficiency while transmitting the peak power, and most of the power amplifiers, when operated in the back-off region, are much less power efficient. Unfortunately, the transmitted power of the OFDM signals is around the average power level most of the time. Therefore, the efficiency of the radio frequency (RF) power amplifier at low output power is a crucial issue for the applications with high peak-to-average power ratio.
The Doherty power amplifier is the power amplifier that can increase the power-added efficiency (PAE) at back-off region. FIG. 1 illustrates the functional block diagram of a conventional Doherty power amplifier 10. The Doherty power amplifier 10 consists of: a main amplifier 12, an auxiliary amplifier 14, a series (cascade) arrangement of a quarter-wave transmission line 16 and the main amplifier 12, and a series (cascade) arrangement of a three-quarter wave transmission line 18 and the auxiliary amplifier 14, wherein the main amplifier 12 is a class-AB power amplifier, while the auxiliary amplifier 14 is a class-C power amplifier. When the Doherty power amplifier 10 operates in low power level region, only the main amplifier 12 operates. When the Doherty power amplifier 10 operates in high power region, the main amplifier 12 saturates and the auxiliary amplifier 14 begins to operate. Through this mechanism and load modulation, the Doherty power amplifier 10 achieves high efficiency at power back-off region.
As shown in FIG. 1, the Doherty power amplifier 10 also has a power splitter 20 for distributing input power to the main amplifier 12 and the auxiliary amplifier 14. The power splitter 20 takes up a large area when implemented with an integrated circuit. Moreover, when the Doherty power amplifier 10 operates at low gigahertz (e.g. 2.4 GHZ), the physical dimensions of the quarter-wave transmission line 16 and 18 become unreasonably large on integrated-circuit chip. Therefore, it is inappropriate to implement the monolithic integrated conventional Doherty power amplifier 10.